In arrays of analog memory cells, such as in Flash memory devices, memory cells may suffer from interference from other memory cells in the array. This interference may introduce read errors and therefore degrade the storage reliability of the memory. Various techniques for interference estimation and cancellation in analog memory cell arrays are known in the art.
For example, PCT International Publication WO 2007/132457, whose disclosure is incorporated herein by reference, describes a method for operating a memory device. The method includes encoding data using an Error Correction Code (ECC) and storing the encoded data as first analog values in respective analog memory cells of the memory device. After storing the encoded data, second analog values are read from the respective memory cells of the memory device in which the encoded data were stored. At least some of the second analog values differ from the respective first analog values. A distortion that is present in the second analog values is estimated. Error correction metrics are computed with respect to the second analog values responsively to the estimated distortion. The second analog values are processed using the error correction metrics in an ECC decoding process, so as to reconstruct the data.
U.S. Patent application Publication 2009/0240872, whose disclosure is incorporated herein by reference, describes a method for data storage that includes defining at least first and second read commands for reading storage values from analog memory cells. The first read command reads the storage values at a first accuracy, and the second read command reads the storage values at a second accuracy, which is finer than the first accuracy. In some embodiments, interference cancellation is applied to a certain group of memory cells by reading the storage values of the potentially-interfering cells using a faster but lower-accuracy read command.
As another example, U.S. Patent application Publication 2009/0034337, whose disclosure is incorporated herein by reference, describes techniques for reading an adjacent cell of a memory array to determine a threshold voltage value of the adjacent cell, the adjacent cell being adjacent to a target cell, and reading the target cell of the memory array using a word-line voltage value based on the threshold voltage value of the adjacent cell. In some embodiments, in response to the command to read a target cell, the memory device may generate an internal read command, in addition to the original read command, to read an adjacent cell before reading the target cell.
U.S. Patent application Publication 2010/0034022, whose disclosure is incorporated herein by reference, describes techniques for compensating for capacitive coupling from storage elements on adjacent bit lines, by adjusting voltages applied to the adjacent bit lines. An initial rough read is performed to ascertain the data states of the bit line-adjacent storage elements, and during a subsequent fine read, bit line voltages are set based on the ascertained states and the current control gate read voltage which is applied to a selected word line. When the current control gate read voltage corresponds to a lower data state than the ascertained state of an adjacent storage element, a compensating bit line voltage is used. Compensation of coupling from a storage element on an adjacent word line can also be provided by applying different read pass voltages to the adjacent word line, and obtaining read data using a particular read pass voltage which is identified based on a data state of the word line-adjacent storage element.
U.S. Pat. No. 7,440,324, whose disclosure is incorporated herein by reference, describes techniques for accounting for electric field coupling in a non-volatile memory cell. To account for this coupling, the read process for a targeted memory cell provides compensation to an adjacent memory cell (or other memory cell) in order to reduce the coupling effect that the adjacent memory cell has on the targeted memory cell. The compensation applied is based on a condition of the adjacent memory cell. To apply the correct compensation, the read process at least partially intermixes read operations for the adjacent memory cell with read operations for the targeted memory cell.
Other example interference cancellation methods are described in PCT International Publication WO 2007/132453, whose disclosure is incorporated herein by reference.